The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to bond pad structures and methods for fabricating bond pad structures.
A chip or die includes integrated circuits formed by front-end-of-line (FEOL) processing and metallization levels of an interconnect structure formed by back-end-of line (BEOL) processing. Chips are then packaged and mounted on a circuit board. Bond pads are commonly utilized to provide mechanical and electrical connections between the last or top metallization level of the chip and the package via bumps.
A bond pad, which is typically composed of aluminum, may be surrounded by an exclusion space that causes mechanical weakness at the chip-to-package interface. High local loads within the package may be transmitted through the solder bump on the bond pad and the underbump metallurgy (UBM) to the BEOL metallization levels. These transmitted forces can increase the risk of under bump failures at the chip-to-package interface, particularly with downward scaling of bond pad dimensions.
Improved bond pad structures and methods for fabricating bond pad structures are needed.